The invention relates to the field of clock and data recovery circuit, and in particular to a LC tank clock driver with automatic tuning.
One of the core blocks in a clock and data recovery circuit is the phase detector. A particular implementation of a phase detector is a half-rate binary phase detector reported by Hauenschild et al., in the paper entitled “A plastic packaged 10 GBPS and data recovery 1:4 demultiplexer with external VCO,” disclose a half-rate implementation that uses two clocks which are orthogonal to each other, wherein each clock is loaded by ten latches. A disadvantage with such an implementation is that the aggregate device and interconnect capacitance on the clocks are substantial.
In high-speed applications, which often have tight jitter specifications, static CMOS logic is rejected in favor of current-mode logic (CML). FIG. 1 illustrates an example of a CML latch 100. A differential clock signal drives the lower differential pair whose inputs are EN 102 and ENB 104. In CMOS technology, the single-ended swing on these clock lines should be greater than 0.4V to guarantee that the differential pair fully directs the current IBLAT 105 to the drain of MEN 106 or MENB 108.
FIG. 2 illustrates circuit 200 for driving the differential clock lines of FIG. 1 using a differential pair with resistive loads. The outputs of the clock driver, denoted as CK 202 and CKB 204 drive the inputs EN (102 of FIG. 1) and ENB (104 of FIG. 1) of the CML latch (100 of FIG. 1). Resistance 206 in the clock driver is in concert with capacitance 208 of the phase detector and creates a pole. The location of this pole is preferably placed as a factor of twice the clock frequency to establish large amplitude signals at the output.
A suitable application for estimating the maximum size of the resistor is OC-192 SONET where the data rate is 9.954 Gbps. The tail current (ITAIL) 210, which should be small for low power, is inversely proportional to the value of the load resistor (RDRV) 206. In OC-192 SONET, the half-rate clock frequency is approximately 5 GHz. A bandwidth of 10 GHz on the clock lines is twice the clock frequency. Accounting for both device and interconnect capacitance, each latch can present a single-ended load on the order of 30 fF. The total capacitance that ten latches present on each clock line is 0.3 pF. A maximum resistance of 53 Ω yields 10 GHz of bandwidth. A voltage swing of 0.4V requires a minimum bias current of 7.5 mA. The total current for two clock drivers is at least 15 mA.
Whatever the precise merits, features, and advantages of the above cited prior art, none of them achieves or fulfills the purposes of the present invention.